Verilog HDL高级数字设计

出版时间:2010-4  出版社:电子工业出版社  作者:西勒提(Michael D.Ciletti)  页数:965  
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前言

  Simplify,Clarify, and Verify  Behavioral modeling with a hardware description language (HDL) is the key to modern design of application-specific integrated circuits (ASICs). Today, most designers use an HDL-based design method to create a high-level, language-based, abstract description of a circuit, and verify its functionality and timing. The language used to teach design methodology in the first edition of this text, IEEE 1464-1995, has undergone two revisions to improve the effectiveness and efficiency of the language: IEEE 1364-2001 followed by a revision in 2005, known as Verilog-2001 and Verilog-2005, respectively.  The motivation behind this edition is basically the same as that which guided the first edition: students preparing to contribute to a productive design team must know how to use a HDL at key stages of the design flow. Thus, there is a need for a course going beyond the basic principles and methods learned in a first course in digital design. This book is written for such a course.  The quantity of books discussing HDLs far exceeds that which was available at the time of the first edition, and most of these are still oriented toward explanations of language syntax, rather than toward design, and are not well-suited for classroom use. Our focus is on design methodology enabled by an HDL. Thus, the language itself has a subordinate role. In this edition, we have made a strong effort to demonstrate by examples the importance of partitioning a digital machine to expose its datapath, status (feedback) signals, and controller (finite state machine).This effort leads, we think, to a much clearer and straightforward approach to designing and verifying complex digital machines. We present an abundance of simulation results, with annotation to help students (1) understand the operation of a sequential machine and (2) appreciate the time-sequential interaction between the signals produced by the controller, the operations in the datapath, and the signals reported back to the controller from the datapath, all with the aim of developing synthesizable, latch-free, race-free designs.

内容概要

本书依据数字集成电路系统工程开发的要求与特点,利用Verilog HDL对数字系统进行建模、设计与验证,对ASIC/FPGA系统芯片工程设计开发的关键技术与流程进行了深入讲解,内容包括:集成电路芯片系统的建模、电路结构权衡、流水、多核微处理器、功能验证、时序分析、测试平台、故障模拟、可测性设计、逻辑综合、后综合验证等集成电路系统的前后端工程设计与实现中的关键技术及设计案例。书中以大量设计实例叙述了集成电路系统工程开发需遵循的原则、基本方法、实用技术、设计经验与技巧。    本书既可作为电子与通信、电子科学与技术、自动控制、计算机等专业领域的高年级本科生和研究生的教材或参考资格,也可用于电子系统设计及数字集成电路设计工程师的专业技术培训。

作者简介

Michael D.Ciletti,科罗拉多大学电气与计算机工程系教授。研究方向包括通过硬件描述语言进行数字系统的建模、综合与验证、系统级设计语言和FPGA嵌入式系统。其著作还有Digital Design,Fourth Edition(其翻译版和影印版均由电子工业出版社出版)。作者曾在惠普、福特微电子和

书籍目录

1 Introduction to Digital Design Methodology   1.1 Design Methodology—An Introduction   1.2 IC Technology Options   1.3 Overview   References 2 Review of Combinational Logic Design   2.1 Combinational Logic and Boolean Algebra   2.2 Theorems for Boolean Algebraic Minimization   2.3 Representation of Combinational Logic   2.4 Simplification of Boolean Expressions   2.5 Glitches and Hazards   2.6 Building Blocks for Logic Design   References   Problems 3 Fundamentals of Sequential Logic Design   3.1 Storage Elements   3.2 Flip-Flops   3.3 Busses and Three-State Devices   3.4 Design of Sequential Machines   3.5 State-Transition Graphs   3.6 Design Example: BCD to Excess-3 Code Converter   3.7 Serial-Line Code Converter for Data Transmission   3.8 State Reduction and Equivalent States   References   Problems 4 Introduction to Logic Design with Verilog   4.1 Structural Models of Combinational Logic   4.2 Logic System, Design Verification, and Test Methodology   4.3 Propagation Delay   4.4 Truth Table Models of Combinational and Sequential Logic with Verilog   References   Problems 5 Logic Design with Behavioral Models of Combinational and Sequential Logic   5.1 Behavioral Modeling   5.2 A Brief Look at Data Types for Behavioral Modeling   5.3 Boolean Equation-Based Behavioral Models of Combinational Logic   5.4 Propagation Delay and Continuous Assignments   5.5 Latches and Level-Sensitive Circuits in Verilog   5.6 Cyclic Behavioral Models of Flip-Flops and Latches   5.7 Cyclic Behavior and Edge Detection   5.8 A Comparison of Styles for Behavioral Modeling   5.9 Behavioral Models of Multiplexers, Encoders, and Decoders   5.10 Dataflow Models of a Linear-Feedback Shift Register   5.11 Modeling Digital Machines with Repetitive Algorithms   5.12 Machines with Multicycle Operations   5.13 Design Documentation with Functions and Tasks: Legacy or Lunacy?   5.14 Algorithmic State Machine Charts for Behavioral Modeling   5.15 ASMD Charts   5.16 Behavioral Models of Counters, Shift Registers, and Register Files   5.17 Switch Debounce, Metastability, and Synchronizers for Asynchronous Signals   5.18 Design Example: Keypad Scanner and Encoder   References   Problems 6 Synthesis of Combinational and Sequential Logic 7 Design and Synthesis of Datapath Controllers 8 Programmable Logic and Storage Devices 9 Algorithms and Architectures for Digital Processors 10 Architectures for Arithmetic Processors 11 Postsynthesis Design Tasks A Verilog Primitives B Verilog Keywords C Verilog Data Types D Verilog Operators E Verilog Language Formal Syntax F Verilog Language Formal Syntax G Additional Features of Verilog H Flip-Flop and Latch Types I Verilog-2001, 2005 J Programming Language Interface K Web sites L Web-Based Resources Index

章节摘录

  HDL-based designs are easier to debug than schematics.A behavioral descrip-tion encapsulating complex functionality hides underlying gate-level detail,so there isless information to cope with in trying to isolate problems in the functionality of thedesign.Furthermore.if the behavioral description is functionally correct.it is a goldstandard for subsequent gate.1evel realizations.  HDL-based designs incorporate documentation within the design by using de-scriptive names,by including comments to clarify intent,and by explicitly specifying ar-chitectural relationships.thereby reducing the volume of documentation that must bekept in other archives.Simulation of a language.based model explicitly specifies thefunctionality of the design.Since the language is a standard.documentation of a designcan be decoupled from a particular vendors tools.  Behavioral modeling is the predominant descriptive style used by industry,en-abling the design of massive chips.Behavioral modeling describes the functionality Dr adesign by specifying what the designed circuit will do.not how to build it in hardware.It specifies the input-output model of a logic circuit and suppresses details about phys-ical,gate-level implementation.  Behavioral modeling encourages designers to(1)rapidly create a behavioral pro-totype of a design(without binding it to hardware details),(2)verify its functionality,and then (3) use a synthesis tool to optimize and map the design into a selected physi-cal technology.If the model has been written in a synthesis-ready style,the synthesistool will remove redundant logic.perform tradeoffs between alternative architecturesand/or multilevel equivalent circuits.and ultimately achieve a design that is compatiblewith area or timing constraints.By focusing the designers attention on the functional-ity that is to be implemented rather than on individual logic gates and their intercon-nections.behavioral modeling provides the freedom to explore alternatives to a designbefore committing it to production.  Aside from its importance in synthesis.behavioral modeling provides flexibilityto a design project by allowing parts of the design to be modeled at difierent levels of abstraction.The Verilog language accommodates mixed levels of abstraction so thatportions of the design that are implemented at the gate level(i-e structurally)can beintegrated and simulated concurrently with other parts of the design that are repre-sented by behavioral descriptions.  1.1.4 Simulation and Functional VerificationThe functionality of a design is verified(Step 4 in Figure 1-1) either by simulation or byformaI methods[7].Our discussion will focus on simulation that is reasonable for the size of circuits we can present here.The design flow iterates back to Step 3 untiI thefunctionality of the design has been verified.The verification process is threefold;itincludes(1)development of a test plan,(2)development of a testbench,and(3)execu-tion of the test.

编辑推荐

  《Verilog HDL高级数字设计(第2版)(英文版)》特色  ·重点讨论现代数字电路系统的设计方法  ·阐述并推广基于Verilog 2001和2005,且可综合的RTL描述和算法建模的设计风格  ·明确指出了可综合和不可综合循环的区别  ·讲述了如何应用ASM和ASMD图进行行为级建模  ·深入讨论基于Verilog 2001和2005的数字处理系统、RISC计算机和各种数据通道控制器、异步和同步FIFO设计的算法和架构及综合的设计实例  ·给出了150多个经过完全验证的实例,对时序分析、故障模拟、测试和可测性设计进行切合实际的讨论  ·含有利用Vetilog 2001和2005编写的具备JTAG和BIST可测功能的实用设计案例  ·每章后均设计了一些涉及面广且难度高的习题  ·包含一套与《Verilog HDL高级数字设计(第2版)(英文版)》内容配套的可适合实验室实验验证的FPGA设计实例,如ALU、可编程电子锁、有FPFO的键盘扫描器、可纠错的串行通信接口、基于SRAM的控制器、异步和同步FIFO设计、存储器及RISC CPU  《Verilog HDL高级数字设计(第2版)(英文版)》支持网站内容包括:所有模型的源文件、仿真实例的测试平台源文件、幻灯片文件、某些工具软件的速  成教案及常见问题解答(FAQ)

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用户评论 (总计32条)

 
 

  •   适合有一定基础的来看,跟其他书在列举Verilog语法的不一样,这本书会以大量的例子,深入地讲解verilog,和生成的电路,思路很清晰,相当推荐
  •   学习verilog不错,很经典,老外写的
  •   感觉技术书还是英文原版的好,例子很多,通俗易懂。实在不行的话可以伴着中文书一起看,不过要注意翻译
  •   英文的,很专业,需慢慢看
  •   内容挺好的,例子很多,讲解很全面
  •   这才是最基础的教材
  •   书到挺快,很好
  •   非常有用的书,学到很多。
  •   纸张还好,外国的书还是跟我们国家的有区别,没那么多抄来抄去的
  •   书不错 国外的书还是比较好的 纸张也不错
  •   书质量不错,推荐去看
  •   LG说看这书受益匪浅
  •   回来仔细看了一下目录,买的目的就是想有机会慢慢了解熟悉下,查缺补漏,毕竟这么厚实的一本书,老外写的思路也想借鉴
  •   内容全面,百读不厌
  •   一本好书,适合稍微打好基础,内容再丰富点就好了。
  •   内容很充实,很值得一看。
  •   一直想买的,终于买到了,看了一下,很好
  •   建议英语水平高的人或者教师看
  •   不是一般的难懂
  •   买了没几天就降了十块钱,有点不爽。。。
  •   一本学习verilog的好书,入门学习不错
  •   这本书只是有时间翻了翻,因为都是比较基础的东西,所以就会全面而不太深入,这个也可以理解,希望以后把书看完后能从中得到些新的知识
  •   个人觉得这是本经典书籍,有待我仔细阅读。。。可以培养专业英语。。书籍运过来的时候,右侧有点破损,如果没有这个问题 就完美了。。。
  •   书写的不错,但是印刷质量和包装是在不敢恭维
  •   纯英文的看起来其实还是有点困难
  •   需要静下心来看,觉得比中文版的好
  •   感觉不错,不过还没看!
  •   虽然现在看不懂。书的纸质不是很好
  •   特价时买的,满百减五十,划算
  •   刚买的书
  •   书印刷质量好,内容也很好
  •   好书啊,适合人手一本
 

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